The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Oct. 24, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsinchu, TW;

Inventors:

Ching-Yen Hsaio, Tainan, TW;

Cheng-Ming Wu, Tainan, TW;

Shih-Lu Hsu, Tainan, TW;

Chien-Hsian Wang, Minxiong Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); H01L 27/11521 (2017.01); H01L 29/06 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/0273 (2013.01); H01L 21/0276 (2013.01); H01L 21/28008 (2013.01); H01L 21/32139 (2013.01); H01L 29/0649 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The method includes forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over the second portion of the conductive layer and an edge portion of the negative photoresist layer, and a thickness of the edge portion decreases in a direction away from the gate stack.


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