The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Dec. 04, 2019
Applicant:

Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;

Inventor:

Zhonghua Li, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/66 (2006.01); H01L 21/28 (2006.01); H01L 23/544 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); H01L 21/28185 (2013.01); H01L 21/28211 (2013.01); H01L 23/544 (2013.01); H01L 21/02247 (2013.01); H01L 21/02252 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01);
Abstract

A PNA temperature monitoring method comprises: Step 1, forming zero mark layer patterns on a tested silicon substrate; Step 2, forming a nitrogen-doped gate oxide by the following process: growing an oxide layer, doping the oxide layer with nitrogen, and carrying out PNA; Step 3, forming overlay layer patterns, and overlaying the overlay layer patterns and the corresponding zero mark layer patterns to form monitoring structures; and Step 4, measuring overlay values of the overlay layer patterns and the corresponding zero mark layer patterns of the monitoring structures, and regulating a PNA temperature according to the measured overlay values. By adoption of the method, the influence of the PNA temperature on a gate oxide in a two-dimensional plane can be monitored, and then the PNA temperature can be regulated to increase product yield.


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