The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2021
Filed:
Nov. 27, 2019
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Yen-Ting Chen, Hsinchu, TW;
Chia-Lin Hsu, Tainan, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/20 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/283 (2006.01); H01L 29/51 (2006.01); H01L 29/06 (2006.01); H01L 23/532 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 21/321 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823462 (2013.01); H01L 21/02263 (2013.01); H01L 21/283 (2013.01); H01L 21/28176 (2013.01); H01L 21/321 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 23/53223 (2013.01); H01L 23/53266 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 29/0611 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/51 (2013.01); H01L 29/511 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7853 (2013.01); H01L 29/78 (2013.01);
Abstract
Metal gate formation methods are disclosed herein for providing metal gates with low work function to enhance semiconductor field effect transistor performance. An exemplary method includes forming a gate dielectric layer on a substrate and a barrier layer over the gate dielectric layer. An outer surface of the barrier layer is treated to increase its roughness. After the outer surface of the barrier layer is roughened, a metal layer is deposited over the barrier layer.