The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Oct. 18, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kwan-Yeob Chae, Hwaseong-si, KR;

Jong-Ryun Choi, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/394 (2020.01); G06F 30/35 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/35 (2020.01); G06F 30/392 (2020.01);
Abstract

To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.


Find Patent Forward Citations

Chae, Kwan-Yeob. (2021). Integrated circuit including load standard cell and method of designing the same (U.S. Patent No. 10977412). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10977412

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…