The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2021
Filed:
Mar. 28, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2019.01); G06F 13/16 (2006.01); G06F 1/3234 (2019.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 1/3206 (2019.01);
U.S. Cl.
CPC ...
G06F 13/161 (2013.01); G06F 1/3206 (2013.01); G06F 1/3253 (2013.01); G06F 9/30101 (2013.01); G06F 9/5005 (2013.01); G06F 2213/0026 (2013.01);
Abstract
Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.