The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Dec. 20, 2018
Applicant:

Advantest Corporation, Tokyo, JP;

Inventors:

Srdjan Malisic, San Jose, CA (US);

Michael Jones, San Jose, CA (US);

Chi Yuan, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 1/02 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2834 (2013.01); G01R 1/025 (2013.01);
Abstract

An automated test equipment (ATE) apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The tester processor is operable to generate commands and data from instructions received from the system controller for coordinating testing of a device under test (DUT), wherein the DUT supports a plurality of non-standard sector sizes and a plurality of protection modes. The FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT, and wherein the at least one hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes.


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