The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2021
Filed:
Jun. 22, 2016
China Electronic Technology Corporation, 24th Research Institute, Chongqing, CN;
Yan Wang, Chongqing, CN;
Tao Liu, Chongqing, CN;
Guang-Bing Chen, Chongqing, CN;
Yu-Xin Wang, Chongqing, CN;
Dong-Bing Fu, Chongqing, CN;
Yu-Jun Yang, Chongqing, CN;
Liang Chen, Chongqing, CN;
Yang Pu, Chongqing, CN;
CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE, Chongqing, CN;
Abstract
The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile