The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Apr. 03, 2019
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

National Chiao Tung University, Hsinchu, TW;

Inventors:

Chao-Hsin Chien, Hsinchu, TW;

Yu-Che Chou, Zhuangwei Township, TW;

Chien-Wei Tsai, Baoshan Township, TW;

Chin-Ya Yi, Taoyuan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/78 (2006.01); H01L 21/225 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7855 (2013.01); H01L 21/2254 (2013.01); H01L 29/66484 (2013.01); H01L 29/66795 (2013.01); H01L 29/66833 (2013.01); H01L 29/7851 (2013.01); H01L 29/792 (2013.01);
Abstract

Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., SiN) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.


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