The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Jan. 06, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Sahil Preet Singh, Hsinchu, TW;

Yen-Huei Chen, Hsinchu County, TW;

Hung-Jen Liao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/412 (2006.01); G11C 11/4097 (2006.01); G11C 7/10 (2006.01); H01L 29/78 (2006.01); G11C 5/14 (2006.01); H01L 27/02 (2006.01); H01L 27/12 (2006.01); G11C 11/413 (2006.01); G11C 7/12 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/147 (2013.01); G11C 5/148 (2013.01); G11C 7/1009 (2013.01); G11C 7/12 (2013.01); G11C 11/4097 (2013.01); G11C 11/412 (2013.01); G11C 11/413 (2013.01); H01L 27/0207 (2013.01); H01L 27/1211 (2013.01); H01L 29/785 (2013.01); H01L 27/1104 (2013.01);
Abstract

A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.


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