The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Feb. 24, 2020
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Nian Yang, Mountain View, CA (US);

Sahil Sharma, San Jose, CA (US);

Piyush Dhotre, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 11/4096 (2006.01); G11C 11/4076 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/46 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 7/222 (2013.01); G11C 11/4076 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/46 (2013.01); G11C 2211/5641 (2013.01);
Abstract

A circuit configured to dynamically adjust data transfer speeds for a non-volatile memory die interface. The circuit includes an initialization circuit, a control circuit, a switch circuit, and a read-write circuit. The initialization circuit is configured to load multi-level cell settings that configure a memory interface for transfer of data for storage cells configured to store more than one bit per storage cell. The control circuit is configured to receive a read command that references single-level storage cells of a memory die. The switch circuit is configured to switch settings for the memory interface from the multi-level cell settings to single level cell settings, in response to receiving the read command. The read-write circuit is configured to read data for the read command from the memory die using the single level cell settings.


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