The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2021
Filed:
Jun. 08, 2020
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Mao-Wei Chiu, Taoyuan, TW;
Ting-Wei Chiang, New Taipei, TW;
Hui-Zhong Zhuang, Kaohsiung, TW;
Li-Chun Tien, Tainan, TW;
Chi-Yu Lu, New Taipei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of manufacturing a semiconductor device (for a layout diagram stored on a non-transitory computer-readable medium) includes generating the layout diagram. The generating the layout diagram includes: placing standard functional cells to partially fill a logic area of the layout diagram according to at least one corresponding schematic design thereby leaving, as unfilled, a spare region in the logic area; selecting a first pitch for additional cells to be placed in the spare region, wherein use of the first pitch minimizes wasted space in the spare region; selecting standard not-yet-programmed (SNYP) spare cells, which are to become at least some of the additional cells, according to the first pitch; and placing the selected SNYP spare cells into the spare region of the layout diagram.