The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2021
Filed:
Mar. 28, 2017
Intel Corporation, Santa Clara, CA (US);
Ned M. Smith, Beaverton, OR (US);
Changzheng Wei, Shanghai, CN;
Songwu Shen, Shanghai, CN;
Ziye Yang, Shanghai, CN;
Junyuan Wang, Shanghai, CN;
Weigang Li, Shanghai, CN;
Wenqian Yu, Shanghai, CN;
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
Technologies for hybrid acceleration of code include a computing device () having a processor (), a field-programmable gate array (FPGA) (), and an application-specific integrated circuit (ASIC) (). The computing device () offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (). The FPGA () performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA () determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (). The ASIC () performs the primitive tasks in response to encapsulation in the buffer, and the FPGA () returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor () or a network interface controller of the computing device ().