The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Aug. 13, 2019
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Manoj Kumar, Westford, MA (US);

Rishabh Gupta, Delhi, IN;

Inderpreet Singh Baweja, Milton, CA;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G06F 16/245 (2019.01);
U.S. Cl.
CPC ...
G01R 31/31704 (2013.01); G01R 31/31703 (2013.01); G01R 31/31705 (2013.01); G06F 16/245 (2019.01);
Abstract

The present disclosure relates to a system and method for debugging in fault simulation associated with an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and performing concurrent fault simulation on a fault to be analyzed associated with the electronic circuit design, wherein the fault has a fault propagation path associated therewith. Embodiments may also include identifying a trace of one or more signals of interest that are in the fault propagation path and generating a faulty database and a good database associated with the one or more signals of interest that are in the fault propagation path. Embodiments may further include identifying one or more differences between the faulty database and the good database.


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