The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

Mar. 30, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kermin E. ChoFleming, Jr., Hudson, MA (US);

Jesmin Jahan Tithi, San Jose, CA (US);

Suresh Srinivasan, Portland, OR (US);

Mahesh A. Iyer, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/24 (2006.01); H04L 12/26 (2006.01); H04L 12/861 (2013.01);
U.S. Cl.
CPC ...
H04L 41/12 (2013.01); H04L 43/0858 (2013.01); H04L 43/16 (2013.01); H04L 49/90 (2013.01);
Abstract

Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.


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