The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

May. 07, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tzu-Cheng Lin, Hsinchu, TW;

Y.Y. Peng, Hsinchu, TW;

Jerry Wang, Hsinchu, TW;

Kewei Zuo, Xinbei, TW;

Chien Rhone Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 19/19 (2006.01); H01L 21/67 (2006.01); G05B 13/02 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67259 (2013.01); G03F 7/70633 (2013.01); G05B 13/027 (2013.01); G05B 19/19 (2013.01); G05B 2219/32335 (2013.01); G05B 2219/45028 (2013.01); G05B 2219/45031 (2013.01);
Abstract

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.


Find Patent Forward Citations

Loading…