The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

Feb. 06, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Zhongze Wang, San Diego, CA (US);

Yandong Gao, San Diego, CA (US);

Xia Li, San Diego, CA (US);

Ye Lu, San Diego, CA (US);

Xiaochun Zhu, San Diego, CA (US);

Xiaonan Chen, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); G11C 11/412 (2006.01); G11C 11/56 (2006.01); G11C 11/419 (2006.01); H01L 27/11 (2006.01); G11C 11/418 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 11/56 (2013.01); H01L 27/1104 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/13023 (2013.01); H01L 2924/1437 (2013.01);
Abstract

A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.


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