The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2021
Filed:
Jan. 21, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sundar Ramani, Bangalore, IN;
Arvind Raman, Austin, TX (US);
Arvind Mandhani, San Francisco, CA (US);
Ashish V. Choubal, Austin, TX (US);
Kalyan Muthukumar, Bangalore, IN;
Ajaya V. Durg, Austin, TX (US);
Samudyatha Chakki, Austin, TX (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/3287 (2019.01); G06F 1/3203 (2019.01); G06F 1/3296 (2019.01); G06F 12/0815 (2016.01); G06F 12/0804 (2016.01); G06F 12/084 (2016.01); G06F 1/324 (2019.01); G06F 1/3234 (2019.01); G06F 12/0808 (2016.01); G06F 12/0831 (2016.01); G06F 12/128 (2016.01); G06F 12/0811 (2016.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3243 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 12/0804 (2013.01); G06F 12/084 (2013.01); G06F 12/0808 (2013.01); G06F 12/0815 (2013.01); G06F 12/0831 (2013.01); G06F 12/128 (2013.01); G06F 12/0811 (2013.01); G06F 12/12 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/314 (2013.01); G06F 2212/621 (2013.01); G06F 2212/70 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08);
Abstract
In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.