The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

Dec. 02, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Hsu-Ting Huang, Hsinchu, TW;

Chih-Shiang Chou, Taoyuan County, TW;

Ru-Gun Liu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 1/36 (2012.01); G03F 1/80 (2012.01); G03F 7/16 (2006.01); G03F 7/20 (2006.01); G03F 7/38 (2006.01); G03F 7/26 (2006.01); G03F 1/78 (2012.01); H01L 21/027 (2006.01); H01L 21/66 (2006.01); G06F 30/20 (2020.01); G06F 30/398 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G03F 1/36 (2013.01); G03F 1/78 (2013.01); G03F 1/80 (2013.01); G03F 7/16 (2013.01); G03F 7/20 (2013.01); G03F 7/26 (2013.01); G03F 7/38 (2013.01); G06F 30/20 (2020.01); G06F 30/398 (2020.01); H01L 21/0277 (2013.01); H01L 22/20 (2013.01); G06F 2119/18 (2020.01);
Abstract

An integrated circuit (IC) method is provided. The method includes building a mask model to simulate an aerial mask image of a mask, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask; calibrating the CLC model using measured wafer data and the calibrated mask model; performing an optical proximity correction (OPC) process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication. Alternatively, the method includes measuring a mask image of a mask optically projected on a wafer with an instrument; calibrating a mask model using the measured mask image; calibrating a CLC model using measured wafer data and the calibrated mask model; and performing an OPC process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication.


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