The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

Dec. 09, 2016
Applicant:

Siltronic Ag, Munich, DE;

Inventors:

Christian Hager, Kastl, DE;

Katharina May, Burghausen, DE;

Christof Weber, Burghausen, DE;

Assignee:

SILTRONIC AG, Munich, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C30B 25/14 (2006.01); C30B 29/06 (2006.01); C30B 25/18 (2006.01); C23C 16/44 (2006.01); C23C 16/02 (2006.01); C30B 25/08 (2006.01); C30B 25/12 (2006.01); C30B 25/16 (2006.01);
U.S. Cl.
CPC ...
C30B 25/14 (2013.01); C23C 16/0236 (2013.01); C23C 16/4405 (2013.01); C30B 25/08 (2013.01); C30B 25/12 (2013.01); C30B 25/165 (2013.01); C30B 25/186 (2013.01); C30B 29/06 (2013.01); H01L 21/0243 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02532 (2013.01); H01L 21/02661 (2013.01);
Abstract

Semiconductor wafers are coated with an epitaxially deposited layer in an epitaxy reactor, wherein at least one semiconductor wafer is arranged on a respective susceptor in the epitaxy reactor and a first deposition gas for coating the at least one semiconductor wafer is conducted through the epitaxy reactor, wherein an etching process in which a first etching gas and a carrier gas are conducted through the epitaxy reactor is carried out before the coating process, and wherein a cleaning process in which a second etching gas and subsequently in particular a second deposition gas are conducted through the epitaxy reactor after a predefinable number of coating processes, wherein for two or more etching processes preceding the respective coating process at least one variable which influences the etching process is set individually. Semiconductor wafers processed thereby have distinctly uniform topology.


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