The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2021
Filed:
Jul. 31, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Ariel Gur, Atlit, IL;
Daniel J. Ragland, Sherwood, OR (US);
Yoav Ben-Raphael, Haifa, IL;
Ernest Knoll, Haifa, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H03L 7/18 (2006.01); H03L 7/14 (2006.01); H03L 7/187 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1803 (2013.01); H03L 7/145 (2013.01); H03L 7/187 (2013.01);
Abstract
Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.