The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Dec. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gil Asa, Zikhron Yaakov, IL;

Assaf Ben-Bassat, Haifa, IL;

Ofir Degani, Nes-Ammin, IL;

Shahar Gross, Nes-Tziona, IL;

Rotem Banin, Even-Yehuda, IL;

Uri Grosglik, Tel Mond, IL;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01); H03K 5/133 (2014.01); H03K 5/156 (2006.01); H03K 5/1534 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
H03K 5/00006 (2013.01); G01R 31/3177 (2013.01); G01R 31/318525 (2013.01); H03K 5/133 (2013.01); H03K 5/1534 (2013.01); H03K 5/1565 (2013.01);
Abstract

This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.


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