The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2021
Filed:
Aug. 07, 2019
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Don Templeton, San Jose, CA (US);
Luke Young Chang, Hillsborough, CA (US);
Narayan Kulshrestha, Fremont, CA (US);
Assignee:
NVIDIA Corp., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/50 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 23/50 (2013.01); H01L 25/0655 (2013.01); H05K 2201/095 (2013.01); H05K 2201/0929 (2013.01); H05K 2201/09781 (2013.01);
Abstract
A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.