The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2021
Filed:
May. 14, 2018
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Qing Cao, Yorktown Heights, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Zhengwen Li, Chicago, IL (US);
Fei Liu, Yorktown Heights, NY (US);
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); G06F 21/44 (2013.01); H01L 29/78 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 27/112 (2006.01); H04L 9/32 (2006.01); H01L 23/544 (2006.01); G06F 21/73 (2013.01); G09C 1/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); G06F 21/44 (2013.01); G06F 21/73 (2013.01); G09C 1/00 (2013.01); H01L 21/84 (2013.01); H01L 23/544 (2013.01); H01L 27/11233 (2013.01); H01L 27/1203 (2013.01); H01L 29/7838 (2013.01); H04L 9/3278 (2013.01); H01L 23/57 (2013.01); H01L 2223/5444 (2013.01);
Abstract
An integrated circuit includes an array of devices with a logic pattern to implement a physically unclonable function (PUF) for chip authentication. The logic pattern is determined in accordance with processing variations during the manufacturing. The array of devices includes one or more components having a first state and one or more components having a second state. A combination of the first and second states provides the logic pattern.