The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

May. 19, 2017
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Kazuki Yamauchi, Kanagawa, JP;

Katsutoshi Suito, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/52 (2006.01); G11C 16/34 (2006.01); G11C 29/04 (2006.01); G11C 16/04 (2006.01); G11C 7/20 (2006.01); G11C 16/26 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G11C 29/52 (2013.01); G06F 12/0246 (2013.01); G11C 7/20 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01); G11C 29/04 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/7203 (2013.01); G11C 2029/0411 (2013.01);
Abstract

An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuitand a controller. The page buffer/reading circuitincludes a first latch circuit Land a second latch circuit L. The first latch circuit Lkeeps data read from the memory cell array. The second latch circuit Lkeeps data transferred from the first latch circuit L. Just after power is turned on or reset, the controllercontrols data of block/pageof the memory cell array to be kept in the second latch circuit Land controls the SFDP data to be kept in the first latch circuit L. The SFDP data or the data of block/pageis serially output according to an input command.


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