The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2021
Filed:
Nov. 20, 2018
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01); H01L 29/788 (2006.01); G11C 11/4093 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 7/1039 (2013.01); G11C 11/4093 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); H01L 29/7885 (2013.01); G11C 11/5628 (2013.01);
Abstract
A memory device includes a memory cell array including a plurality of strings, a peripheral circuit coupled to the memory cell array and configured for sequentially performing a program voltage apply operation, a program verify operation, and a hole injection operation on the plurality of strings, and a control logic configured for controlling an operation of the peripheral circuit, wherein the control logic controls the operation of peripheral circuit to generate Gate Induced Drain Leakage (GIDL) at a channel under a select transistor of each of the plurality of strings during the hole injection operation.