The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2021
Filed:
Mar. 23, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 11/419 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01); G11C 5/06 (2006.01); G11C 11/408 (2006.01); G11C 5/02 (2006.01); H01L 27/11 (2006.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/025 (2013.01); G11C 5/066 (2013.01); G11C 5/147 (2013.01); G11C 5/148 (2013.01); G11C 7/12 (2013.01); G11C 7/222 (2013.01); G11C 11/4087 (2013.01); H01L 27/11 (2013.01); G06F 30/392 (2020.01); G11C 2207/2227 (2013.01);
Abstract
An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.