The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Aug. 01, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bryan K. Casper, Portland, OR (US);

Stephen R. Mooney, Mapleton, UT (US);

David Dunning, Portland, OR (US);

Mozhgan Mansuri, Hillsboro, OR (US);

James E. Jaussi, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H03M 13/15 (2006.01); G11C 29/12 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1076 (2013.01); G11C 5/02 (2013.01); G11C 29/12 (2013.01); H03M 13/152 (2013.01); H01L 2224/16145 (2013.01); H03M 13/15 (2013.01);
Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.


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