The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Mar. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mark Dechene, Hillsboro, OR (US);

Srikanth Srinivasan, Portland, OR (US);

Matthew Merten, Hillsboro, OR (US);

Ammon Christiansen, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/22 (2006.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 9/22 (2013.01); G06F 9/3838 (2013.01); G06F 9/4881 (2013.01);
Abstract

A processor and method are described for a multi-level reservation station. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of operations; a reservation station comprising a plurality of entries to store a corresponding plurality of operations to be executed on one or more of the functional units, the reservation station comprising: a first RS level to hold a first subset of the plurality of operations which are ready for execution by one or more functional units or which are expected to be ready for execution by the functional units; a second RS level to hold a second subset of the plurality of operations which are not expected to be ready for execution by the functional units; operation evaluation circuitry to evaluate operations in the first RS level and, responsive to identifying one or more operations which are not expected to be ready for execution, to cause the one or more operations to be moved from the first RS level to the second RS level.


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