The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Mar. 05, 2019
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Maicol Cannella, Antibes, FR;

Aurelien Larie, Le Cannet, FR;

Stefano Dal Toso, Antibes, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/02 (2006.01); H03F 3/24 (2006.01); H03F 3/68 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0277 (2013.01); H03F 3/245 (2013.01); H03F 3/45179 (2013.01); H03F 3/68 (2013.01); H03F 2200/378 (2013.01); H03F 2200/451 (2013.01); H03F 2200/513 (2013.01); H03F 2200/516 (2013.01); H03F 2200/546 (2013.01); H03F 2203/21106 (2013.01); H03F 2203/45024 (2013.01); H03F 2203/45186 (2013.01);
Abstract

Power amplifiers and related methods are disclosed having configurable switched mode operation in a high-power mode of operation and a low-power mode of operation. The power amplifiers have a first cascode amplifier coupled to receive a positive differential input and a second cascode amplifier coupled to receive a negative differential input. The first and second cascode amplifiers include output stages and first/second input stages. The first input stages and the second input stages are enabled in a high-power mode of operation. The first input stages are disabled and the second input stages are enabled during a low-power mode of operation. For further embodiments, a switchable clamp operates in the low-power mode to clamp a voltage output for the second input stages. For further embodiments, the output stages are provided a variable voltage bias or are coupled to tunable capacitances that are varied between the low-power and high-power modes.


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