The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Nov. 05, 2019
Applicant:

Global Power Technologies Group, Inc., Lake Forest, CA (US);

Inventors:

Rahul R. Potera, Irvine, CA (US);

Vipindas Pala, San Jose, CA (US);

Tony Witt, Lake Forest, CA (US);

Assignee:

SEMIQ INCORPORATED, Lake Forest, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1033 (2013.01); H01L 29/1608 (2013.01); H01L 29/7832 (2013.01);
Abstract

A silicon carbide MOSFET includes first and second source regions respectively disposed in the first and second well regions. Each of the first and second source regions extends up to a top surface of the substrate. First and second channel regions of the respective first and second well regions laterally separate the first and second source regions from a JFET region by a channel length. The first and second channel regions extend up to the top surface. The first and second channel regions are each arranged in a wave-shaped pattern at the top surface of the substrate. The wave-shaped pattern extends in first and second lateral directions. In an on-state, current flows laterally from the first and second source regions to the JFET region, and then in a vertical direction down through an extended drain region to the drain region.


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