The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Jul. 12, 2019
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Byung In Lee, Hwaseong-si, KR;

Hee Joung Park, Seoul, KR;

Keon Soo Shim, Icheon-si, KR;

Sang Heon Lee, Chungcheongbuk-do, KR;

Jae Il Tak, Seoul, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01);
Abstract

A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.


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