The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Dec. 13, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

William V. Huott, Holmes, NY (US);

Adam J. McPadden, Underhill, VT (US);

Anuwat Saetow, Austin, TX (US);

David D. Cadigan, Fairfield, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G06F 11/106 (2013.01); G06F 11/1032 (2013.01); G06F 11/1076 (2013.01); H03K 3/037 (2013.01);
Abstract

A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of LLlatches connected in a chain, each LLlatch includes an Llatch and an Llatch with the Llatch having a connected output monitored for a flip. A single Ldetect circuit exclusive OR (XOR) is connected to each Llatch. An Ldetect circuit XOR tree includes an input connected to a true output of a respective Llatch in the chain. An Lclock (LCK) trigger circuit is connected to an output of the Ldetect circuit XOR tree and is shared across each of the plurality of LLlatches for correcting bit flip errors.


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