The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Dec. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mark Elzinga, Shingle Springs, CA (US);

Youngmin Park, Folsom, CA (US);

Michael Bichan, Toronto, CA;

Michael W. Altmann, Folsom, CA (US);

Noam Familia, Modiin, IL;

Vadim Levin, Mevaseret Zion, IL;

Dror Lazar, Kiryat Bialik, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/10 (2006.01); H03M 3/00 (2006.01); H03L 7/099 (2006.01); H03L 7/18 (2006.01); H03L 7/187 (2006.01);
U.S. Cl.
CPC ...
H03L 7/10 (2013.01); H03L 7/0991 (2013.01); H03L 7/18 (2013.01); H03L 7/187 (2013.01); H03M 3/50 (2013.01);
Abstract

Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.


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