Source synchronous interface with selectable delay on source and delay on destination control

Abstract

A transmitter circuit for use in a source synchronous type interface includes a flip-flop having a data input configured to receive serial data, a clock input configured to receive a source clock and a data output coupled to a data line. A first multiplexer has a first input configured to receive the source clock, a second input configured to receive a phase shifted clock (shifted by ninety degrees from the source clock), and a clock output coupled to a clock line. A control circuit operates to control selection by the first multiplexer of the source clock as a transmit clock sent over the clock line for a delay on clock at destination implementation. Alternatively, the control circuit causes selection by the first multiplexer of the phase shifted clock as the transmit clock sent over the clock line if the system is configured for a delay on clock at source implementation.