The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Apr. 20, 2020
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Kyung Suk Oh, Cupertino, CA (US);

Ian P. Shaeffer, Los Gatos, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); G06F 13/40 (2006.01); G11C 11/4093 (2006.01); H03K 19/0175 (2006.01); G11C 11/401 (2006.01); G11C 11/419 (2006.01); G11C 16/26 (2006.01); G11C 11/41 (2006.01); G11C 11/4063 (2006.01); G11C 11/413 (2006.01); G11C 11/417 (2006.01); G11C 16/06 (2006.01); G11C 16/32 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0005 (2013.01); G06F 3/0605 (2013.01); G06F 3/0659 (2013.01); G06F 3/0685 (2013.01); G06F 13/4086 (2013.01); G11C 11/401 (2013.01); G11C 11/4063 (2013.01); G11C 11/4093 (2013.01); G11C 11/41 (2013.01); G11C 11/413 (2013.01); G11C 11/417 (2013.01); G11C 11/419 (2013.01); G11C 16/06 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); H03K 19/017545 (2013.01);
Abstract

A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.


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