The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2021
Filed:
Jul. 18, 2018
No.24 Research Institute of China Electronics Technology Group Corporatio, Chongqing, CN;
Daiguo Xu, Chongqing, CN;
Gangyi Hu, Chongqing, CN;
Ruzhang Li, Chongqing, CN;
Jian'an Wang, Chongqing, CN;
Guangbing Chen, Chongqing, CN;
Dongbing Fu, Chongqing, CN;
Shiliu Xu, Chongqing, CN;
Tao Liu, Chongqing, CN;
Jie Pu, Chongqing, CN;
Zhihua Feng, Chongqing, CN;
Abstract
The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage. In the present disclosure, a substrate bootstrap technology of MOS transistors is used, thereby reducing on resistances of the MOS transistors and improving the comparator speed; threshold voltages of the input transistors of the comparator are reduced, transconductance of the input transistors is increased, thereby reducing equivalent input noise of the comparator, and as a common-mode voltage of the comparator changes, a comparison delay changes relatively little.