The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Feb. 11, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Byung-Jun Park, Yongin-si, KR;

Chang-Rok Moon, Seoul, KR;

Seung-Hun Shin, Suwon-si, KR;

Seong-Ho Oh, Incheon, KR;

Tae-Seok Oh, Seoul, KR;

June-Taeg Lee, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 27/146 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 21/768 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 27/1464 (2013.01); H01L 27/1469 (2013.01); H01L 27/14634 (2013.01); H01L 21/76805 (2013.01); H01L 25/50 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.


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