The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Aug. 02, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Shigeki Kobayashi, Kuwana Mie, JP;

Taro Shiokawa, Nagoya Aichi, JP;

Masahisa Sonoda, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); G11C 5/06 (2006.01); H01L 27/11524 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11519 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 5/063 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01);
Abstract

A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.


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