The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Apr. 18, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Takaaki Iwai, Yokkaichi, JP;

Makoto Koto, Yokkaichi, JP;

Sayako Nagamine, Yokkaichi, JP;

Ching-Huang Lu, Fremont, CA (US);

Wei Zhao, San Jose, CA (US);

Yanli Zhang, San Jose, CA (US);

James Kai, Santa Clara, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11519 (2017.01); H01L 21/762 (2006.01); H01L 27/11565 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/762 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.


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