The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Jan. 08, 2019
Applicants:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Abderrezak Marzaki, Aix en Provence, FR;

Arnaud Regnier, Les Tallades, FR;

Stephan Niel, Meylan, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/94 (2006.01); H01L 29/66 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/0214 (2013.01); H01L 21/76224 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/0805 (2013.01); H01L 29/66181 (2013.01); H01L 29/945 (2013.01);
Abstract

A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.


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