The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Aug. 14, 2019
Applicant:

Invensense, Inc., San Jose, CA (US);

Inventors:

Dongyang Kang, San Jose, CA (US);

Bongsang Kim, Mountain View, CA (US);

Bei Zhu, Los Gatos, CA (US);

Ian Flader, Redwood City, CA (US);

Assignee:

InvenSense, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 7/00 (2006.01); B81C 3/00 (2006.01); B81C 1/00 (2006.01); B81B 1/00 (2006.01);
U.S. Cl.
CPC ...
B81B 7/007 (2013.01); B81B 1/004 (2013.01); B81B 7/0006 (2013.01); B81C 1/00063 (2013.01); B81C 1/00095 (2013.01); B81C 1/00166 (2013.01); B81C 1/00301 (2013.01); B81C 3/001 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2203/033 (2013.01); B81B 2203/04 (2013.01); B81B 2207/096 (2013.01); B81C 2203/036 (2013.01); B81C 2203/038 (2013.01);
Abstract

A method includes fusion bonding a first side of a MEMS wafer to a second side of a first handle wafer. A TSV is formed from a first side of the first handle wafer to the second side of the first handle wafer and into the first MEMS wafer. A dielectric layer is formed on the first side of the first handle wafer. A tungsten via is formed in the dielectric layer. Electrodes are formed on the dielectric layer. A second MEMS wafer is eutecticly bonded with a first eutectic bond to the electrodes, wherein the TSV electrically connects the first MEMS wafer to the second MEMS wafer. Standoffs are formed on a second side of the first MEMS wafer. A CMOS wafer is eutecticly bonded with a second eutectic bond to the standoffs, wherein the second eutectic bond includes different materials than the first eutectic bond.


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