The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2021
Filed:
Mar. 10, 2016
Sicpa Holding SA, Prilly, CH;
Lucia Giovanola, Ivrea, IT;
Silvia Baldi, Turin, IT;
Anna Merialdo, Ivrea, IT;
Paolo Schina, Turin, IT;
SICPA HOLDING SA, Prilly, CH;
Abstract
The present application relates to a method of manufacturing an ink-jet printhead comprising: providing a silicon substrate () including active ejecting elements (); providing a hydraulic structure layer () for defining hydraulic circuits configured to enable a guided flow of ink; providing a silicon orifice plate () having a plurality of nozzles () for ejection of the ink; assembling the silicon substrate () with the hydraulic structure layer () and the silicon orifice plate (); wherein providing the silicon orifice plate () comprises: providing a silicon wafer () having a planar extension delimited by a first surface () and a second surface () on opposite sides of the silicon wafer (); performing a thinning step at the second surface () so as to remove from the second surface () a central portion () having a preset height (H), the silicon wafer () being formed, following the thinning step, by a base portion () having a planar extension and a peripheral portion () extending from the base portion (), transversally with respect to the planar extension of the base portion (); and forming in the silicon wafer () a plurality of through holes, each defining a respective nozzle () for ejection of the ink. The method according to the present invention is characterized in that the silicon wafer () is a silicon-on-insulator wafer, wherein the silicon-on-insulator wafer comprises a silicon device layer () adjacent to the first surface (), a silicon handle layer () adjacent to the second surface () and an insulator layer () in-between.