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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10940671 B1

PDFFull Text
Date of Patent:
Mar. 09, 2021

Filed:

Jul. 18, 2016

Substrate for electrical circuits and method for producing a substrate of this type

Applicant:

Rogers Germany Gmbh, Eschenbach, DE;

Inventors:

Andreas Meyer, Wenzenbach, DE;

Karsten Schmidt, Eschenbach, DE;

Assignee:

ROGERS GERMANY GMBH, Eschenbach, DE;

Attorney:

Cantor Colburn LLP

Primary Examiner:

Alexandre F Ferre

Int. Cl.
CPC ...
B32B 9/00 (2006.01); B32B 15/04 (2006.01); B32B 15/12 (2006.01); B32B 15/20 (2006.01); B32B 29/00 (2006.01); B32B 29/08 (2006.01); B32B 5/12 (2006.01); B32B 5/20 (2006.01); B32B 7/12 (2006.01); B32B 9/04 (2006.01); B32B 9/06 (2006.01); C25D 11/00 (2006.01); C25D 11/04 (2006.01); C25D 17/12 (2006.01); H01L 23/373 (2006.01); H05K 1/05 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 3/46 (2006.01); C25D 11/08 (2006.01);
U.S. Cl.
CPC ...
B32B 9/005 (2013.01); B32B 5/12 (2013.01); B32B 5/20 (2013.01); B32B 7/12 (2013.01); B32B 9/041 (2013.01); B32B 9/06 (2013.01); B32B 15/043 (2013.01); B32B 15/12 (2013.01); B32B 15/20 (2013.01); B32B 29/002 (2013.01); B32B 29/08 (2013.01); C25D 11/005 (2013.01); C25D 11/04 (2013.01); C25D 17/12 (2013.01); H01L 23/3735 (2013.01); H05K 1/0201 (2013.01); H05K 1/0313 (2013.01); H05K 1/053 (2013.01); H05K 3/4688 (2013.01); B32B 2255/06 (2013.01); B32B 2255/205 (2013.01); B32B 2255/26 (2013.01); B32B 2255/28 (2013.01); B32B 2264/107 (2013.01); B32B 2307/202 (2013.01); B32B 2307/206 (2013.01); B32B 2307/54 (2013.01); B32B 2457/08 (2013.01); B32B 2605/00 (2013.01); C25D 11/08 (2013.01); H05K 2201/0116 (2013.01); H05K 2201/0338 (2013.01); H05K 2203/0315 (2013.01); H05K 2203/11 (2013.01); H05K 2203/1126 (2013.01);
Abstract

A substrate () for electrical circuits, comprising at least one metal layer () and a paper ceramic layer (), which is joined face to face with the at least one metal layer () and has a top side and bottom side (), wherein the paper ceramic layer () has a large number of cavities in the form of pores. Especially advantageously, the at least one metal layer () is connected to the paper ceramic layer () by means of at least one glue layer (), which is produced by applying at least one glue (″) to the metal layer () and/or to the paper ceramic layer (), wherein the cavities in the form of pores in the paper ceramic layer () are filled at least at the surface by means of the applied glue (″).

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