The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2021
Filed:
Mar. 13, 2019
International Business Machines Corporation, Armonk, NY (US);
Kamal K. Sikka, Poughkeepsie, NY (US);
Fee Li Lie, Albany, NY (US);
Kevin Winstel, East Greenbush, NY (US);
Ravi K. Bonam, Albany, NY (US);
Iqbal Rashid Saraf, Cobleskill, NY (US);
Dario Goldfarb, Dobbs Ferry, NY (US);
Daniel Corliss, Waterford, NY (US);
Dinesh Gupta, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.