The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Mar. 14, 2019
Applicant:

Disco Corporation, Tokyo, JP;

Inventors:

Youngsuk Kim, Tokyo, JP;

Byeongdeck Jang, Tokyo, JP;

Assignee:

DISCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H05K 1/18 (2006.01); H01L 23/522 (2006.01); H01L 23/36 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/544 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/367 (2013.01); H01L 23/49822 (2013.01); H01L 23/544 (2013.01); H01L 21/565 (2013.01); H01L 24/48 (2013.01); H01L 2223/54433 (2013.01); H01L 2224/48227 (2013.01);
Abstract

A semiconductor package manufacturing method includes the steps of bonding a plurality of semiconductor chips to the front side of a wiring substrate, next supplying a sealing compound to the front side of the wiring substrate to thereby form a sealing layer from the sealing compound on the front side of the wiring substrate, thereby forming a package substrate, next holding the package substrate on a holding tape, next cutting the front side of the resin layer by using a profile grinding tool to thereby form a plurality of ridges and grooves on the front side of the resin layer, thereby increasing the surface area of the front side of the resin layer, and next dividing the package substrate along each division line to obtain a plurality of individual semiconductor packages.


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