The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2021
Filed:
Jun. 18, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Kiran Pangal, Fremont, CA (US);
Prashant S. Damle, Portland, OR (US);
Rajesh Sundaram, Folsom, CA (US);
Shekoufeh Qawami, El Dorado Hills, CA (US);
Julie M. Walker, El Dorado Hills, CA (US);
Doyle Rivers, El Dorado Hills, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); H03M 13/05 (2006.01); H03M 13/27 (2006.01); H03M 13/00 (2006.01); G06F 3/06 (2006.01); H03M 13/15 (2006.01); H03M 13/19 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1076 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G06F 11/1044 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); H03M 13/05 (2013.01); H03M 13/27 (2013.01); H03M 13/6508 (2013.01); H03M 13/152 (2013.01); H03M 13/1515 (2013.01); H03M 13/19 (2013.01);
Abstract
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.