The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Nov. 18, 2019
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

Robert J. Mayell, Los Altos, CA (US);

Yueming Wang, Gilroy, CA (US);

Roger Colbeck, Ottawa, CA;

Hartley Fred Horwitz, Ottawa, CA;

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/335 (2006.01); H02M 3/158 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
H02M 3/33507 (2013.01); G06F 1/12 (2013.01); H02M 3/1584 (2013.01); H02M 2003/1586 (2013.01);
Abstract

A controller configured for use in a power converter includes a multiplexer that receives a startup clock signal and a request clock signal. The multiplexer selects the startup signal or the request clock signal to generate a clock signal. A startup clock generates the startup clock signal to control a switching frequency of a primary switching circuit during a startup condition. A request clock generates the request clock signal in response to a request signal to control the switching frequency of the primary switching circuit after the startup condition. A control circuit receives the clock signal to generate a drive signal control the switching frequency of the primary switching circuit. The control circuit selects the startup clock signal during the startup condition. The control circuit receives an indication in the request signal of an end of an undervoltage condition and then selects the request clock signal after the startup condition.


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