The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Mar. 28, 2019
Applicant:

Ememory Technology Inc., Hsinchu, TW;

Inventors:

Chen-Hao Po, Hsinchu County, TW;

Cheng-Te Yang, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 5/14 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 21/28 (2006.01); H01L 27/11517 (2017.01); G11C 7/08 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/408 (2013.01); G11C 5/147 (2013.01); G11C 7/065 (2013.01); G11C 7/08 (2013.01); G11C 7/12 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 21/022 (2013.01); H01L 21/0217 (2013.01); H01L 21/0226 (2013.01); H01L 21/02107 (2013.01); H01L 21/02109 (2013.01); H01L 21/02112 (2013.01); H01L 21/02225 (2013.01); H01L 21/02247 (2013.01); H01L 21/28202 (2013.01); H01L 27/11517 (2013.01); H01L 29/0603 (2013.01); H01L 29/0607 (2013.01); H01L 29/0638 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08);
Abstract

A differential type non-volatile memory circuit comprising a differential sensing circuit, a differential data line pair, a memory cell array, and a differential bit line pair is provided. The differential sensing circuit has a differential input terminal pair and a differential output terminal pair. The differential data line pair is electrically connected to the differential input terminal pair of the differential sensing circuit. The memory cell array has at least one differential non-volatile memory cell configured to store data. The differential bit line pair is electrically connected between the memory cell array and the differential data line pair. When logic states of the differential output terminal pair start to be different in a read operation phase of the memory cell array, the differential sensing circuit and the differential data line pair are disconnected.


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