The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Nov. 27, 2019
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Shin-Cheng Lin, Tainan, TW;

Chih-Yen Chen, Tainan, TW;

Chia-Ching Huang, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/402 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/41758 (2013.01); H01L 29/41775 (2013.01); H01L 29/42316 (2013.01); H01L 29/7787 (2013.01);
Abstract

A semiconductor structure includes a substrate, a gate structure disposed on the substrate, a source structure and a drain structure disposed on opposite sides of the gate structure, and a first dielectric layer. The gate structure includes a gate electrode disposed on the substrate and a gate metal layer electrically connected to the gate electrode and serving as a gate field plate. The source structure includes a source electrode disposed on the substrate and a first source metal layer electrically connected to the source electrode and extending in the direction from the gate electrode to the drain structure. The first dielectric layer is disposed on the gate metal layer. The electric potential of the first source metal layer is different from that of the gate metal layer. The first source metal layer exposes at least a portion of the first dielectric layer directly above the gate metal layer.


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