logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10930565 B1

PDFFull Text
Expired
Date of Patent:
Feb. 23, 2021

Filed:

Nov. 01, 2018

Iii-v cmos co-integration

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

HsinYu Tsai, San Jose, CA (US);

Renee T. Mo, Yorktown Heights, NY (US);

Cheng-Wei Cheng, White Plains, NY (US);

Ko-Tao Lee, Yorktown Heights, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Cantor Colburn LLP

Robert Sullivan

Primary Examiner:

Andres Munoz

Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/8258 (2006.01); H01L 21/84 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/161 (2006.01); H01L 29/20 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/02546 (2013.01); H01L 21/8258 (2013.01); H01L 21/82385 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 27/0924 (2013.01); H01L 27/1203 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 29/161 (2013.01); H01L 29/20 (2013.01); H01L 29/66522 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01);
Abstract

A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.

Find Patent Forward Citations

Tsai, HsinYu. (2021). Iii-v cmos co-integration (U.S. Patent No. 10930565). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10930565

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…